1. Field of the Invention
This invention relates to a DLL (Delay Locked Loop) circuit, and particularly relates to a DLL circuit which generates an internal signal having a predetermined time difference relative to an external clock signal and a semiconductor device (for example, a synchronous type semiconductor device) having this DLL circuit.
2. Related Art
Recently, DDR-SDRAM (Double Data Rate—Synchronous Dynamic Random Access Memory) is widely known as a high speed synchronous type semiconductor memory device. When read operation is performed in the DDR-SDRAM, each edge timing of a DQ signal being input/output data and a DQS signal for determining a timing to capture input/output data needs to be controlled to have an accurate phase relationship with an external reference clock. Therefore, a DLL circuit for generating the DQS and DQ signals by phase control based on the reference clock signal (for example, see JP-2003-91331).
A general DLL circuit used in the conventional synchronous type semiconductor memory device has, for example, a configuration shown in FIG. 10. In the DLL circuit shown in FIG. 10, the external reference clock signal CLK is input to a delay circuit 102 through an input circuit 101 and delayed by a delay time according to a control signal C supplied from a delay control circuit 104. A signal D from the delay circuit 102 is input to a DQ output circuit 107 and a DQS output circuit 108 as an internal clock signal CLK0 through a buffer D. The DQ signal is generated by the DQ output circuit 107 and the DQS signal is generated by the output circuit 108, so as to be output to the outside. Meanwhile, the internal clock signal CLK0 is also input to a dummy output circuit 106 having the same transmission characteristics as the DQ output circuit 107 and the DQS output circuit 108, and a feedback clock signal RCLK having the same phase as the DQ and DQS signals is output. In a phase comparison circuit 103, phases of the reference clock signal CLK and the feedback clock signal RCLK are compared, and the delay control circuit 104 is controlled in a direction where both phases are equal. Such a configuration allows to obtain the DQ and DQS signals which maintain stable synchronization with the reference clock signal CLK.
However, the reference clock signal CLK input to the DLL circuit from the outside does not always have a normal waveform, and jitter is assumed to occur at a certain timing. FIG. 11 shows operation waveforms of the DLL circuit of FIG. 10 in a state in which jitter occurs in the reference clock signal CLK. As shown in FIG. 11, arising timing of the reference clock signal CLK delays at fourth cycle by time A, so that cycle-to-cycle jitter occurs in which the period deviates between a predetermined cycle and a subsequent cycle. Under the influence thereof, the delay of the same time n is transmitted on rising timings of the signal D1, the internal clock signal CLK0, the DQS and DQ signals. Therefore, it is a problem that size of an effective window used for capturing input/output data is reduced by an amount of the time Δ, and correspondingly, the possibility of data latching failure increases.